(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of applying backside cleaning of a substrate after deposition of a layer of gate oxide in order to create high dielectric constant gate oxides.
(2) Description of the Prior Art
Conventional methods of creating CMOS devices use gate electrodes of polysilicon that is deposited and patterned over a layer of gate oxide. In many applications the surface of the patterned and etched layer of polysilicon is salicided in order to meet requirements of low contact sheet resistivity. In designing CMOS devices, the performance of these devices is improved by reducing the gate length of the gate electrode or by reducing the thickness of the layer of gate oxide that is first formed over a semiconductor surface, which is typically the surface of a silicon substrate. The gate length of CMOS devices is the distance between the source and the drain regions of the device where this distance extends underneath the gate electrode. With the continued decrease in device dimensions, the gate length for sub-micron devices has been decreased to 0.25 xcexcm or less. The invention addresses the era where gate length dimension approach 0.1 xcexcm, for these applications of gate electrodes the Effective Oxide Thickness (EOT) is less than about 14 Angstrom. As gate dielectrics are reduced to this thickness, a practical and theoretical limit is being approached to the thermal oxidation of a silicon surface for the formation of a layer of gate oxide. In order to meet this challenge, the semiconductor industry is developing materials that can be used as replacement of the thermal oxides that are typically used for the layer of gate dielectric.
For gate electrodes that are created with a layer of gate dielectric having an EOT of 14 Angstrom, the leakage current of the gate dielectric, typically comprising oxide or oxynitride, is in excess of 10 A/cm2. This results in high power consumption of the gate electrode and in concerns of gate reliability, thus having a serious negative impact on the electrical performance of the gate electrode.
For this reason, high-k metal oxide materials have been proposed as a potential material to replace the currently used thermal oxide gate dielectrics. Since the dielectric constant of metal oxide material is higher than the dielectric constant of thermal oxide, a thicker layer of metal oxide can be deposited while still achieving the required a value of EOT that is comparable to the EOT value of a thinner layer of thermal gate oxide material. The thicker layer of metal gate oxide reduces the gate-to-channel leakage current without having a negative impact on CMOS device performance and is therefore advantageous. It has for instance been found that a relatively thick layer of metal oxide gate dielectric, having a thickness of about 85 Angstrom, provides the equivalent electrical performance of a thermal oxide gate dielectric having a thickness of about 18 Angstrom.
The prior art processing that applies new materials for the layer of gate dielectric has for instance used tantalum pentoxide or the chemically growing of a layer of silicon dioxide over which a layer of tantalum pentoxide is formed. These method however have shown to introduce a series of parasitic capacitances that are interposed between the layer of the gate electrode overlying the layer of tantalum pentoxide and the underlying silicon substrate. The apparent improvement that has been introduced by the introduction of the layer of tantalum pentoxide is therefore counteracted by the concurrent introduction of parasitic capacitances, the latter negating the beneficial effects of the layer of tantalum pentoxide. It is therefore of advantage to provide a method of creating a layer of gate dielectric such that no negative side effects are introduced. The invention provides such a method.
U.S. Pat. No. 6,020,243 (Wallace et al.) shows a Zr or HF Oxide high k gate dielectric and process.
U.S. Pat. No. 5,403,434 (Moslehi) shows a wafer clean process using HF.
U.S. Pat. No. 6,115,867 (Nakashima) shows a process to clean both sides of a wafer.
U.S. Pat. No. 6,020,024 (Maiti) shows a process for hi-k metal oxides.
A principle objective of the invention is to provide a method of creating a layer of gate dielectric for application in gate electrodes of deep sub-micron dimensions.
Another objective of the invention is to provide a method of creating a layer of gate dielectric for application in gate electrodes of deep sub-micron dimensions whereby the level of contaminants is reduced.
In accordance with the objectives of the invention a new method is provided for the creation of a layer of gate dielectric for gate electrodes having deep sub-micron dimensions. Under the first embodiment of the invention, a layer of high-k dielectric constant material is deposited over the front surface of the substrate. A first backside cleaning of the wafer is performed, using solutions of Hydrofluoric acid (HF) with different concentrations for this first backside cleaning. A layer of polysilicon is deposited over the surface of the layer of high-k dielectric constant material, the layer of deposited polysilicon and the layer of high-k dielectric constant material are patterned and etched, creating a layer of gate dielectric comprising a high-k dielectric constant material over which a patterned layer of polysilicon remains in place forming a layer of a polysilicon gate electrode. Optionally, a second backside cleaning of the wafer is performed, using solutions of HF with different concentrations for this second backside cleaning.
Under the second embodiment of the invention a layer of polysilicon is deposited over the surface of the layer of high-k dielectric constant material, a first backside cleaning of the wafer is performed, using mixture solutions that are best suited for removal of contaminants of high-k dielectric constant material and polysilicon for this first backside cleaning. The layer of deposited polysilicon and the layer of high-k dielectric constant material are patterned and etched, creating a layer of gate dielectric comprising a high-k dielectric constant material over which a patterned layer of polysilicon remains in place forming a layer of a polysilicon gate electrode. Optionally, a second backside cleaning of the wafer is performed, using mixture solutions that are best suited for removal of contaminants of high-k dielectric constant material and polysilicon for this first backside cleaning.
Under the third embodiment of the invention a layer of high-k dielectric constant material is deposited over the front surface of the substrate, a layer of polysilicon is in-situ deposited over the surface of the layer of high-k dielectric constant material. The layer of deposited polysilicon and the layer of high-k dielectric constant material are patterned and etched, creating a layer of gate dielectric comprising a high-k dielectric constant material over which a patterned layer of polysilicon remains in place forming a layer of a polysilicon gate electrode. A backside cleaning of the wafer is performed, using mixture solutions that are best suited for removal of contaminants of high-k dielectric constant material and polysilicon for this backside cleaning.